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Advanced-control timers (TIM1&TIM8)
Figure 77. Capture/compare channel (example: channel 1 input stage)
TI1F_ED
to the slave mode controller
RM0008
TI1
f DTS
filter
downcounter
TI1F
Edge
Detector
TI1F_Rising
TI1F_Falling
0
1
TI1FP1
TI2FP1
01
10
IC1
divider
/1, /2, /4, /8
IC1PS
(from slave mode
ICF[3:0]
TIMx_CCMR1
CC1P
TIMx_CCER
TI2F_rising
(from channel 2)
TI2F_falling
(from channel 2)
0
1
TRC
controller)
11
CC1S[1:0] ICPS[1:0]
TIMx_CCMR1
CC1E
TIMx_CCER
The output stage generates an intermediate waveform which is then used for reference:
OCxRef (active high). The polarity acts at the end of the chain.
Figure 78. Capture/compare channel 1 main circuit
APB Bus
MCU-peripheral interface
8
8
read CCR1H S
read CCR1L
R
read_in_progress
write_in_progress
Capture/compare preload register
output
capture_transfer c ompare_transfer mode
S write CCR1H
write CCR1L
R
CC1S[1]
CC1S[0]
CC1S[1]
CC1S[0]
IC1PS
input
mode
Capture/compare shadow register
capture
comparator
OC1PE
OC1PE
UEV
TIM1_CCMR1
(from time
base unit)
CC1E
CNT>CCR1
270/995
CC1G
TIM1_EGR
Counter
Doc ID 13902 Rev 9
CNT=CCR1
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